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| RF6100-4 0 Typical Applications * 3V CDMA US-PCS Handset * 3V CDMA2000/1XRTT US-PCS Handset * 3V CDMA2000/1X-EV-DO US-PCS Handset * Spread-Spectrum System Product Description 1 3V 1900MHZ LINEAR POWER AMPLIFIER MODULE 1.40 1.25 0.800 1.000 TYP 0.000 0.600 Optimum Technology Matching(R) Applied Si BJT Si Bi-CMOS InGaP/HBT GaAs HBT SiGe HBT GaN HEMT GaAs MESFET Si CMOS SiGe Bi-CMOS Package Style: Module (4mmx4mm) Features * Input/Output Internally Matched@50 * 28.5dBm Linear Output Power * 39% Peak Linear Efficiency * 28dB Linear Gain VCC1 1 RF IN 2 GND 3 VMODE 4 VREG 5 Bias 10 VCC2 9 GND 8 RF OUT 7 GND 6 GND * -48dBc ACPR @ 1.25MHz Ordering Information RF6100-4 3V 1900MHz Linear Power Amplifier Module RF6100-4 PCBA Fully Assembled Evaluation Board Functional Block Diagram RF Micro Devices, Inc. 7628 Thorndike Road Greensboro, NC 27409, USA 3.000 The RF6100-4 is a high-power, high-efficiency linear amplifier module specifically designed for 3V handheld systems. The device is manufactured on an advanced third generation GaAs HBT process, and was designed for use as the final RF amplifier in 3V IS-95/CDMA 2000 1X handheld digital cellular equipment, spread-spectrum systems, and other applications in the 1850MHz to 1910MHz band. The RF6100-4 has a digital control line for low power applications to lower quiescent current. The device is self-contained with 50 input and output that is matched to obtain optimum power, efficiency and linearity. The module is a 4mmx4mm land grid array with backside ground. The RF6100-4 is footprint compatible with industry standard 4mmx4mm CDMA modules, and requires only one decoupling capacitor. 4.00 0.10 Dimensions in mm. 4.00 0.10 Shaded areas represent pin 1 location. 0.100 TYP 0.500 0.550 TYP 0.806 3.200 3.350 3.500 TYP 3.900 TYP 0.450 0.075 1 3.903 TYP 3.453 TYP 3.053 2.653 2.205 TYP 1.805 TYP 1.475 TYP 1.455 0.155 0.103 TYP 0.000 3.850 3.050 2.825 2.600 2.418 2.053 1.953 1.353 0.953 0.553 0.155 Tel (336) 664 1233 Fax (336) 664 0454 http://www.rfmd.com Rev A0 031217 2-1 RF6100-4 Absolute Maximum Ratings Parameter Supply Voltage (RF off) Supply Voltage (POUT 31dBm) Control Voltage (VREG) Input RF Power Mode Voltage (VMODE) Operating Temperature Storage Temperature Rating +8.0 +5.2 +3.9 +10 +3.5 -30 to +110 -40 to +150 Unit V V V dBm V C C Caution! ESD sensitive device. RF Micro Devices believes the furnished information is correct and accurate at the time of this printing. However, RF Micro Devices reserves the right to make changes to its products without notice. RF Micro Devices does not assume responsibility for the use of the described product(s). Parameter High Gain Mode (VMODE Low) Operating Frequency Range Linear Gain Second Harmonics Third Harmonics Maximum Linear Output Linear Efficiency Maximum ICC ACPR @ 1.25MHz ACPR @ 2.25MHz Input VSWR Output VSWR Stability Noise Power Specification Min. Typ. Max. Unit Condition T=25oC Ambient, VCC =3.4V, VREG =2.8V, VMODE =0V, and POUT =28.5dBm for all parameters (unless otherwise specified). 1850 26 28 -35 -40 39 535 -48 -62 2:1 1910 31 -30 28.5 35 600 -46 -56 6:1 10:1 MHz dB dBc dBc dBm % mA dBc dBc No oscillation>-70dBc No damage At 80MHz offset. T=25oC Ambient, VCC =3.4V, VREG =2.8V, VMODE =2.8V, and POUT =28.5dBm for all parameters (unless otherwise specified). -139 dBm/Hz Low Gain Mode (VMODE High) Operating Frequency Range Linear Gain Second Harmonics Third Harmonics Maximum Linear Output Linear Efficiency ACPR @1.25MHz ACPR @2.25MHz Maximum ICC Linear Gain Input VSWR Output VSWR Stability 1850 25 27 -35 -40 39 -48 -60 140 26 2:1 1910 31 -30 MHz dB dBc dBc dBm % dBc dBc mA dB 28.5 35 -46 -56 165 POUT =16dBm POUT =16dBm No oscillation>-70dBc No damage 6:1 10:1 2-2 Rev A0 031217 RF6100-4 Parameter Power Supply Supply Voltage High Gain Idle Current Low Gain Idle Current VREG Current VMODE Current RF Turn On/Off Time DC Turn On/Off Time Total Current (Power Down) VREG Low Voltage (Power Down) VREG High Voltage (Recommended) VREG High Voltage (Operational) VMODE Voltage VMODE Voltage 3.2 60 50 3.4 75 65 1.1 250 1.2 2 0.2 2.8 4.2 90 80 2 500 6 40 5 0.5 2.95 3.0 0.5 3.0 V mA mA mA uA uS uS uA V V V V V Specification Min. Typ. Max. Unit Condition T=25C Ambient VMODE =low and VREG =2.8V VMODE =high and VREG =2.8V VCC =3.4V, VREG =2.8V 0 2.75 2.7 0 2.0 High Gain Mode Low Gain Mode Rev A0 031217 2-3 RF6100-4 Pin 1 2 3 4 5 6 7 8 9 10 Pkg Base Function VCC1 RF IN GND VMODE VREG GND GND RF OUT GND VCC2 GND Description First stage collector supply. A low frequency decoupling capacitor (e.g., 4.7F) may be required. RF input internally matched to 50. This input is internally AC-coupled. Ground connection. Connect to package base ground. For best performance, keep traces physically short and connect immediately to ground plane. For nominal operation (High Power Mode), VMODE is set LOW. When set HIGH, devices are biased lower to improve efficiency. Regulated voltage supply for amplifier bias. In Power Down mode, both VREG and VMODE need to be LOW (<0.5V). Ground connection. Connect to package base ground. For best performance, keep traces physically short and connect immediately to ground plane. Ground connection. Connect to package base ground. For best performance, keep traces physically short and connect immediately to ground plane. RF Output internally matched to 50. This output is internally AC-coupled. Ground connection. Connect to package base ground. For best performance, keep traces physically short and connect immediately to ground plane. Output stage collector supply. A low frequency decoupling capacitor (e.g., 4.7F) is required. Ground connection. The backside of the package should be soldered to a top side ground pad which is connected to the ground plane with multiple vias. The pad should have a short thermal path to the ground plane. Interface Schematic 2-4 Rev A0 031217 RF6100-4 Evaluation Board Schematic (Download Bill of Materials from www.rfmd.com.) VCC1 C2 4.7 F 50 strip 1 2 3 4 VMODE C4 4.7 F 5 P1 1 VREG C3 4.7 F P1-2 2 3 P1-4 4 P2 1 2 P2-3 3 4 P2-5 6 Bias 10 9 8 7 C1 22 F 50 strip J2 RF OUT VCC2 J1 RF IN GND VCC1 GND VCC2 GND GND VREG GND GND 5 CON5 VMODE 5 CON5 Rev A0 031217 2-5 RF6100-4 PCB Design Requirements PCB Surface Finish The PCB surface finish used for RFMD's qualification process is electroless nickel, immersion gold. Typical thickness is 3inch to 8inch gold over 180inch nickel. PCB Land Pattern Recommendation PCB land patterns are based on IPC-SM-782 standards when possible. The pad pattern shown has been developed and tested for optimized assembly at RFMD; however, it may require some modifications to address company specific assembly processes. The PCB land pattern has been developed to accommodate lead and package tolerances. PCB Metal Land and Solder Mask Pattern A = 0.40 (mm) Sq. Typ. Pin 1 3.40 Typ. 2.55 Typ. 1.90 Typ. 1.50 Typ. 0.85 Typ. 0.00 A A A 3.60 Typ. 2.75 Typ. 2.35 Typ. Pin 1 A = 0.55 (mm) Sq. Typ. B = 2.65 x 3.95 (mm) A A A A A B A A A A A 3.40 Typ. 2.55 Typ. Dimensions in mm. 1.70 Typ. 0.85 Typ. 0.00 A A A 1.70 Typ. 1.05 Typ. 0.65 Typ. 0.20 Typ. 0.20 Typ. 0.00 0.45 Typ. 2.95 Typ. 3.60 Typ. Metal Land Pattern Figure 1. PCB Metal Land Pattern and Solder Mask Pattern (Top View) Thermal Pad and Via Design The PCB land pattern has been designed with a thermal pad that matches the exposed die paddle size on the bottom of the device. Thermal vias are required in the PCB layout to effectively conduct heat away from the package. The via pattern has been designed to address thermal, power dissipation and electrical requirements of the device as well as accommodating routing strategies. The via pattern used for the RFMD qualification is based on thru-hole vias with 0.203mm to 0.330mm finished hole size on a 0.5mm to 1.2mm grid pattern with 0.025mm plating on via walls. If micro vias are used in a design, it is suggested that the quantity of vias be increased by a 4:1 ratio to achieve similar results. 2-6 0.00 Solder Mask Pattern Rev A0 031217 1.70 |
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